The instruction decode PLA in the Z80 microprocessor

	*	e	f	g	0	/0	1	/1	2	/2	6	/6	7	/7	3	/3	4	/4	5	/5	Instruction		Description
98	.	1	.	.	.	1	.	1	1	.	.	1	.	1	.	.	.	1	1	.	1101x011	e	out (*),a/in a,(*)
97	.	1	.	.	.	1	.	1	1	.	.	1	.	1	.	.	.	1	.	1	1111x011	e	di/ei
96	.	.	.	1	1	.	.	1	.	1	.	1	1	.	.	.	.	.	.	.	01xxx110	g	im n
95	.	1	.	.	1	.	.	1	.	1	.	1	1	.	1	.	.	1	.	1	01110110	e	halt
GND
94	.	.	.	1	1	.	1	.	1	.	1	.	.	1	.	.	.	.	.	1	101xx000	g	ldi/ldir/ldd/lddr
93	.	.	.	1	.	1	1	.	1	.	1	.	.	1	.	.	.	.	.	1	101xx001	g	cpi/cpir/cpd/cpdr
92	.	1	.	.	.	1	.	1	.	1	1	.	1	.	1	.	.	1	.	1	00110111	e	scf
91	.	.	.	1	.	.	.	1	1	.	1	.	.	1	.	.	.	.	.	1	101xx01x	g	inx/outx/inxr/otxr
90	.	1	.	.	1	.	1	.	1	.	1	.	1	.	1	.	.	1	1	.	00010000	e	djnz *
89	.	1	.	.	.	1	.	1	.	1	1	.	1	.	.	1	.	1	.	1	00111111	e	ccf
88	1	.	.	.	.	.	.	.	.	.	.	.	.	.	.	1	1	.	.	1	xx101xxx	d	101 (XOR)
87	.	.	.	1	.	1	.	1	.	1	.	1	1	.	.	.	.	1	1	.	0101x111	g	ld a,i / ld a,r
GND
86	1	.	.	.	.	.	.	.	.	.	.	.	.	.	1	.	.	1	.	1	xx110xxx	d	110 (OR)
85	1	.	.	.	.	.	.	.	.	.	.	.	.	.	1	.	1	.	.	1	xx100xxx	d	100 (AND)
--- bit 3
84	1	.	.	.	.	.	.	.	.	.	.	.	.	.	1	.	1	.	1	.	xx000xxx	d	000 (ADD)
83	.	.	.	1	.	1	.	1	.	1	.	1	1	.	.	.	.	1	1	.	0101x111	g	ld a,i / ld a,r at top, clk at bottom
82	.	.	.	1	1	.	1	.	.	1	.	1	1	.	.	.	.	.	.	.	01xxx100	g	neg
81	.	1	.	.	.	1	.	1	.	1	1	.	1	.	.	1	1	.	.	1	00101111	e	cpl
80	1	.	.	.	.	.	.	.	.	.	.	.	.	.	.	1	1	.	1	.	xx001xxx	d	001 (ADC)
GND
79	1	.	.	.	.	.	.	.	.	.	.	.	.	.	.	1	.	1	1	.	xx011xxx	d	011 (SBC)
78	1	.	.	.	.	.	.	.	.	.	.	.	.	.	1	.	.	1	1	.	xx010xxx	d	010 (SUB)
--- bit 4
77	.	1	.	.	.	1	.	1	.	1	1	.	1	.	1	.	1	.	.	1	00100111	e	daa
76	1	.	.	.	.	.	.	.	.	.	.	.	.	.	.	1	.	1	.	1	xx111xxx	d	111 (CP)
75	.	1	.	.	.	1	1	.	.	1	1	.	1	.	.	.	.	.	.	.	00xxx101	e	dec
74	.	.	1	.	.	.	.	.	.	.	.	1	.	1	.	.	.	.	.	.	11xxxxxx	f	cb:set
73	.	.	1	.	.	.	.	.	.	.	1	.	.	1	.	.	.	.	.	.	10xxxxxx	f	cb:res
72	.	.	1	.	.	.	.	.	.	.	.	1	1	.	.	.	.	.	.	.	01xxxxxx	f	cb:bit
GND
71	.	1	.	.	.	1	.	1	.	1	1	.	1	.	.	.	.	.	1	.	000xx111	e	rlca/rla/rrca/rra
70	.	.	1	.	.	.	.	.	.	.	1	.	1	.	.	.	.	.	.	.	00xxxxxx	f	cb:rotate/shift
69	.	1	.	.	.	1	1	.	1	.	1	.	1	.	.	1	.	.	.	.	00xx1001	e	add hl,rr
68	.	.	.	1	1	.	.	1	1	.	.	1	1	.	.	.	.	.	.	.	01xxx010	g	ed:adc/sbc
67	.	.	.	1	1	.	1	.	1	.	.	1	1	.	.	.	.	.	.	.	01xxx000	g	in
66	.	1	.	.	.	.	1	.	.	1	1	.	1	.	.	.	.	.	.	.	00xxx10x	e	inc/dec
65	.	1	.	.	.	.	.	.	.	.	1	.	.	1	.	.	.	.	.	.	10xxxxxx	e	add/sub/and/or/xor/cmp a,r
64	.	1	.	.	1	.	.	1	.	1	.	1	.	1	.	.	.	.	.	.	11xxx110	e	add/sub/and/or/xor/cmp a,imm
---
GND
63	.	1	.	.	1	.	.	1	.	1	1	.	1	.	.	.	.	.	.	.	00xxx110	e	ld r,*
62	.	.	1	.	.	.	.	.	.	.	.	.	.	.	.	.	.	.	.	.	xxxxxxxx	f	all f
---
61	.	1	.	.	.	.	.	.	.	.	.	1	1	.	.	.	.	.	.	.	01xxxxxx	e	ld
60	.	.	.	1	.	1	.	1	.	1	.	1	1	.	.	.	1	.	.	1	0110x111	g	rrd/rld
---
---
---
GND
59	1	1	.	.	.	.	.	.	.	.	.	1	1	.	1	.	.	1	.	1	01110xxx	ce	ld (hl),r (and hlt)
58	1	1	.	.	1	.	.	1	.	1	.	1	1	.	.	.	.	.	.	.	01xxx110	ce	ld r, (hl) (and hlt)
---
57	.	.	.	1	.	1	.	1	.	1	.	1	1	.	.	.	1	.	1	.	0100x111	g	ld i,a / ld r,a
56	.	1	.	.	.	1	.	1	.	1	.	1	.	1	.	.	.	.	.	.	11xxx111	e	rst, bit 3 at bottom
55	.	.	1	.	1	.	.	1	.	1	.	.	.	.	.	.	.	.	.	.	xxxxx110	f	cb: op (hl)
54	1	.	1	.	.	.	.	.	.	.	.	.	.	.	.	.	.	.	.	.	xxxxxxxx	bf
--- bit /0
53	.	1	.	.	.	.	1	.	.	1	1	.	1	.	1	.	.	1	.	1	0011010x	e	inc/dec (hl)
GND
52	.	1	.	.	1	.	.	1	.	1	1	.	.	1	.	.	.	.	.	.	10xxx110	e	add/sub/and/or/xor/cp (hl)
--- bit 4
51	.	1	.	.	.	1	1	.	.	1	.	1	.	1	.	1	1	.	.	1	11101101	e	EXTD
--- bit /1
--- bit /2
50	.	1	.	.	1	.	.	1	.	1	1	.	1	.	1	.	.	1	.	1	00110110	e	ld (hl),*
49	1	.	.	.	.	1	.	1	1	.	.	1	.	1	.	1	1	.	1	.	11001011	b	BITS
48	.	1	.	.	1	.	1	.	1	.	1	.	1	.	.	.	.	.	.	1	001xx000	e	jr cc,*
GND
47	.	1	.	.	1	.	1	.	1	.	1	.	1	.	.	1	.	1	1	.	00011000	e	jr *
46	.	.	.	1	.	1	1	.	.	1	.	1	1	.	.	.	.	.	.	.	01xxx101	g	retx
45	.	1	.	.	1	.	1	.	1	.	.	1	.	1	.	.	.	.	.	.	11xxx000	e	ret cc
44	.	1	.	.	.	1	.	1	1	.	.	1	.	1	.	1	1	.	1	.	11001011	e	BITS
43	.	1	.	.	1	.	.	1	1	.	.	1	.	1	.	.	.	.	.	.	11xxx010	e	jp cc,**
42	.	1	.	.	1	.	1	.	.	1	.	1	.	1	.	.	.	.	.	.	11xxx100	e	call cc,**
41	.	1	.	.	.	1	1	.	.	1	.	1	.	1	.	1	.	1	.	.	11x11101	e	IX/IY
40	1	1	.	.	1	.	.	1	.	1	1	.	1	.	1	.	.	1	.	1	00110110	be	ld (hl),*
GND
39	.	1	.	.	1	.	1	.	1	.	1	.	1	.	.	1	1	.	1	.	00001000	e	ex af,af'
38	.	1	.	.	1	.	.	1	1	.	1	.	1	.	.	.	.	1	.	1	0011x010	e	ld (**),a/a,(**)
37	.	1	.	.	.	1	.	1	1	.	.	1	.	1	.	.	.	1	1	.	1101x011	e	out (*),a/a,(*)
36	.	1	.	.	1	.	.	1	1	.	1	.	1	.	.	.	.	.	1	.	000xx010	e	ld(rr),a/a,(rr)
35	.	1	.	.	.	1	1	.	1	.	.	1	.	1	.	1	1	.	1	.	11001001	e	ret
34	.	.	.	1	.	1	1	.	1	.	.	1	1	.	.	.	.	.	.	.	01xxx001	g	out (c),r
33	.	.	.	1	.	1	.	1	1	.	.	1	1	.	1	.	.	.	.	.	01xx0011	g	ld (**),rr
32	.	.	.	1	.	1	.	1	.	1	.	1	1	.	.	.	.	.	1	.	010xx111	g	ld i,a/a,i/r,a/a,r
GND
---
31	.	.	.	1	.	1	.	1	1	.	.	1	1	.	.	.	.	.	.	.	01xxx011	g	ld rr,**/**,rr
30	.	1	.	.	1	.	.	1	1	.	1	.	1	.	.	.	1	.	.	1	0010x010	e	ld hl,**/**,hl
29	.	1	.	.	.	1	.	1	1	.	.	1	.	1	1	.	1	.	1	.	11000011	e	jp
28	.	1	.	.	.	1	.	1	1	.	.	1	.	1	1	.	.	1	1	.	11010011	e	out(*),a
--- bit 3
27	.	.	.	1	.	.	1	.	1	.	.	1	1	.	.	.	.	.	.	.	01xxx00x	g	in/out
26	.	1	.	.	1	.	1	.	1	.	1	.	1	.	1	.	.	1	1	.	00010000	e	djnz
GND
25	.	1	.	.	.	1	.	1	.	1	1	.	1	.	.	.	.	.	1	.	000xx111	e	rlca/rla/rrca/rra
24	.	1	.	.	.	1	1	.	.	1	.	1	.	1	.	1	1	.	1	.	11001101	e	call
---
23	.	1	.	.	.	1	1	.	.	.	.	1	.	1	1	.	.	.	.	.	11xx0x01	e	push/pop
---
22	1	.	.	.	.	1	.	1	1	.	.	1	.	1	.	1	1	.	1	.	11001011	a	BITS
21	.	.	.	1	1	.	.	1	1	.	1	.	.	1	.	.	.	.	.	1	101xx010	g	inx/inxr
GND
20	.	.	.	1	.	1	.	1	1	.	1	.	.	1	.	.	.	.	.	1	101xx011	g	outx/otxr
---
19	.	.	.	1	.	1	1	.	1	.	1	.	.	1	.	.	.	.	.	1	101xx001	g	cpi/cpir/cpd/cpdr
18	.	.	.	1	1	.	1	.	1	.	1	.	.	1	.	.	.	.	.	1	101xx000	g	ldi/ldir/ldd/lddr
17	.	1	.	.	1	.	.	1	.	1	1	.	1	.	.	.	.	.	.	.	00xxx110	e	ld r,*
GND
16	.	1	.	.	.	1	1	.	.	1	.	1	.	1	1	.	.	.	.	.	11xx0101	e	push rr
15	.	.	.	1	.	1	.	1	.	1	.	1	1	.	.	.	1	.	.	1	0110x111	g	rrd
---
14	.	1	.	.	.	1	.	1	1	.	1	.	1	.	.	1	.	.	.	.	00xx1011	e	dec rr
13	.	1	.	.	1	.	.	1	1	.	1	.	1	.	1	.	.	.	.	.	00xx0010	e	ld (rr),a/ld(**),a/ld(**),hl
12	.	.	.	1	1	.	1	.	1	.	1	.	.	1	.	.	.	.	.	1	101xx000	g	ldi/ldir/ldd/lddr
11	.	.	.	1	.	1	1	.	1	.	1	.	.	1	.	.	.	.	.	1	101xx001	g	cpi/cpir/cpd/cpdr
10	.	1	.	.	.	1	.	1	1	.	.	1	.	1	1	.	1	.	.	1	11100011	e	ex (sp),hl
GND
9	.	1	.	.	.	1	.	1	1	.	1	.	1	.	.	.	.	.	.	.	00xxx011	e	inc/dec rr
8	.	1	.	.	1	.	.	1	1	.	1	.	1	.	.	.	.	.	1	.	000xx010	e	ld (rr),a/a,(rr)
7	.	1	.	.	.	1	1	.	1	.	1	.	1	.	1	.	.	.	.	.	00xx0001	e	ld rr,**
6	.	1	.	.	.	1	1	.	1	.	.	1	.	1	.	1	1	.	.	1	11101001	e	jp (hl)
5	.	1	.	.	.	1	1	.	1	.	.	1	.	1	.	1	.	1	.	1	11111001	e	ld sp,hl
4	.	.	.	1	.	1	.	1	.	1	.	1	1	.	.	.	.	.	1	.	010xx111	g	ld x,a/a,x
GND
3	.	1	.	.	.	1	1	.	.	1	.	1	.	1	.	1	.	1	.	.	11x11101	e	IX/IY
2	.	1	.	.	.	1	.	1	1	.	.	1	.	1	.	1	1	.	.	1	11101011	e	ex de,hl
1	.	1	.	.	.	1	1	.	1	.	.	1	.	1	.	1	.	1	1	.	11011001	e	exx
0	.	.	.	1	.	.	.	.	1	.	1	.	.	1	.	.	1	.	.	1	1010x0xx	g	ldx/cpx/inx/outx

The table has input lines running vertically and output lines running horizontally. A 1 indicates the presence of a transistor and a . indicates the absence. If a transistor is present, the corresponding input line must be low or else the output will be pulled low.

Most of the input lines are instruction bits or complemented instruction bits. The first four input lines are special. The first input line is split into four segments with four different inputs labeled a, b, c, and d. The next three input lines are labeled e, f, and g.

a and b are the same line, low if there was an IX/IY prefix. Line c is just pla95, indicating HALT. This line "removes" HALT from the LD (HL) sequence that it would otherwise be in. Line d is from pla64 and pla65; it indicates an ALU operation where the operation is selected by bits b5, b4, b3. e is low for a regular instruction (no prefix). f is low for a cb-prefixed instruction. g is low for a ed-prefixed instruction.

The output lines are numbered 0 to 98. The instruction column shows what intruction value(s) will successfully match the PLA line, followed by the 'special' control line value. The description field summarizes the matching instructions.

GND indicates a ground line passing through the PLA, --- indicates a signal line passing through the PLA, and a blank row indicates an empty space in the PLA.

This was generated from the reverse-engineering images images of the Z80 created by the Visual 6502 team. The PLA appears in the image as the rectangular strip about 1/4 of the way in from the left side.